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Novel Technique to Reduce Substrate Tilt & Improve Bondline Control between AlN Substrate and AlSiC Baseplate in IGBT Modules


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Large area solder joints in multi-chip power semiconductor packages experience fatigue caused by the periodic straining of the interconnection layers during thermal excursions as the device is operational. These stresses lead to delamination and cracks within the solder layer after many thermal cycles which increase the junction-to-case thermal resistance and ultimately lead to early device failure


This is a companion discussion topic for the original entry at https://eepower.com/assemblies/novel-technique-reduce-substrate-tilt-improve-bondline-control-between-aln-substrate-and